1. Field of the Invention
The present invention generally relates to circuits for controlling an electric current, and particularly relates to a cascode current mirror circuit.
2. Description of the Related Art
The cascode current mirror circuit has features such as extremely high output resistance and relatively high operation speed, and is used as an important analog circuit element. In the cascode current mirror circuit, transistors are arranged in tandem, which ends up lowering the voltage margin of the circuit. There is a circuit construction known to overcome this shortcoming and suitable for low-voltage operation (e.g., Non-patent Document 1). Such circuit construction is widely use.
FIG. 1 is a circuit diagram showing an example of a related-art cascode current mirror circuit. The circuit of FIG. 1 includes a current source I1, a current source I3, and NMOS transistors M11, M12, M21, M22, and M3, In the following description, a threshold voltage of a transistor is denoted as Vth, a gate-source voltage denoted as Vgs, and a drain-source voltage denoted as Vds. In order to discriminate each transistor, further, Vth, Vgs, and Vds are suffixed to indicate the threshold voltage, the gate-source voltage, and the drain-source voltage of a corresponding transistor. In order for a transistor to operate in the saturation region, the drain-source voltage needs to be no less than Vgs-Vth. This minimum necessary drain-source voltage (Vgs-Vth) is defined as Vdsat.
The transistors M11 and M21 have their gates connected to each other to make up a current mirror circuit. The transistors M12 and M22 also have their gates connected to each other to make up a current mirror circuit. An electric current (in the amount of I1) generated by the reference current source I1 flows through the transistors M11 and M12. The transistors M21 and M22 constituting a current outputting circuit operate in the substantially same bias conditions as M11 and M12 to output the electric current I2. With a ratio between the respective sizes of the transistors M11 and M12 and a ratio between the respective sizes of the transistors M12 and M22 being set to a desired ratio, it is possible to generate the output current I2 having the desired ratio relative to the reference current I1.
In this configuration, a rise in a potential V1 prompts the current running through the transistor M11 to become greater than the reference current I1. In response, the drain potential of the transistor M12 is pulled down. The drain potential of the transistor M12 is connected to the potential V1, so that feedback control is effected to pull down the potential V1. A fall in the potential V1, on the other hand, prompts the current running through the transistor M11 to become smaller than the reference current I1. In response, the drain potential of the transistor M12 is pulled up. The drain potential of the transistor M12 is connected to the potential V1, so that feedback control is effected to pull up the potential V1.
In order for the circuit of FIG. 1 to operate properly, all the transistors in the circuit need to operate in the saturation region. In the following, a description will be given of the conditions required for M11 and M12 to operate in the saturation region.
The current source I3 and the transistor M3 generate a gate-node voltage V2 of the transistor M12. The conditions required for M11 and M12 to operate in the saturation region are Vdsat11<Vds11 and Vdsat12<Vds12. Since Vdsat11=V1−Vth11 and Vds12=V1−Vds11, at least Vdsat12<Vth11 needs to be satisfied.
The transistors M12 and M22 are in the identical bias conditions, so that Vdsat of M22 is substantially equal to Vdsat12. With regard to frequency response characteristics of the transistor M22 used in the cascode stage in the current outputting circuit of the cascode current mirror circuit, a cut-off frequency indicative of such characteristics can be approximated by gm/Cp by using the gm of the transistor and a parasitic capacitance Cp. The mutual conductance gm in the saturation region can be regarded as approximately proportional to (W/L) Vdsat by using a gate width W, gate length L, and Vdsat of the transistor. Cp can be regarded as approximately proportional to WL. Accordingly, the cut-off frequency gm/Cp indicative of the frequency response characteristics can be regarded as approximately proportional to Vdsat/L2.
From the above description, it is understood that the frequency response characteristics of the transistor M22 can be improved by making L shorter or by increasing Vdsat22 that is the Vdsat of M22. Since the minimum gate length is determined by the process technology for the transistor, there is a limit to the shortening of L. Also, there are cases in which it is preferable to have L longer than the minimum gate length for the purpose of avoiding a short-channel effect created by the shortening of the transistor gate length. Accordingly, there is a need to increase Vdsat22 as much as necessary if desired frequency response characteristics are to be achieved for M22.
[Non-patent Document] J. N. Babanezhad and R. Gregorian, “A Programmable Gain/Loss Circuit,” IEEE J. of Solid-State Circuits, Vol. 22, No. 6, pp. 1082-1090, December 1987
When the circuit of FIG. 1 is used, as described above, a limit Vth11 exists as a maximum possible value of Vdsat22, i.e., Vdsat12. A further description will be given here with regard to this point. Vdsat12 needs to be increased in order to achieve desired frequency response characteristics. In order to increase Vdsat12, it is necessary to increase Vgs12. If the gate voltage of the transistor M12 is raised for this purpose, it becomes necessary to raise the drain voltage V1 of M12 so as to secure an operation in the saturation region for M12. Since the voltage V1 is also the gate voltage of the transistor M11, a widening of the gap between the gate voltage V1 and Vth11 makes it difficult to secure an operation in the saturation region for M11. Accordingly, there is an upper limit to Vdsat12 in relation to Vth11 when an attempt is made to raise Vdsat12.
As a result, the frequency response characteristics of the transistor M22 have limitations. It is thus not possible to design a circuit that is faster than certain speed.
The transistor threshold voltage Vth is a device-dependent voltage. Basically, it cannot be set freely, and varies depending on process conditions and temperature. The value of Vdsat12 that is settable at the time of design is thus a lower limit of the range defined by varying process conditions and temperature. Namely, the speed of the circuit has its limit corresponding to this lower limit determined according to the circuit construction. The above description has been provided with reference to an example in which the cascode current mirror circuit is implemented by use of NMOS transistors. The same also applies in the case of a cascode current mirror circuit implemented by use of PMOS transistors.
Accordingly, there is a need for a cascode current mirror circuit that can achieve desired speed while securing an operation in the saturation region.